An Ultra-Low Power Harmonic-Free Multiphase DLL Using a Frequency-Estimation Selector

This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range and locking speed of the ADMDLL, we proposed the adaptive successive approximation register-controlled (ASAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed leakagereduced delay unit can save 12% leakage power consumption and provide good linearity versus digital control words. After locking, the dynamic frequency monitor circuit is proposed to compensation phase error caused by PVT variations. The proposed ADMDLL is capable of operating in wide supply voltage range from 0.3V to 1.0V. The power dissipation is only 520μW at 1.25GHz/1.0V, and 2.1μW at 13MHz/0.3V, respectively. This work is based on UMC 90nm standard CMOS technology.